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吴比 ( 副研究员 ) 赞
的个人主页 http://faculty.nuaa.edu.cn/wubi/zh_CN/index.htm
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招生学科专业：
电子信息 -- 【招收硕士研究生】 -- 集成电路学院
集成电路科学与工程 -- 【招收硕士研究生】 -- 集成电路学院

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[31] .Erase-Hidden and Drivability-Improved Magnetic Non-Volatile Flip-Flops With NAND-SPIN Devices.[J]:IEEE Transactions on Nanotechnology,2020,19:446 - 454
[32] .Evaluation of Ultrahigh-Speed Magnetic Memories Using Field-Free Spin–Orbit Torque.[J]:IEEE Transactions on Magnetics,2018,54(11)
[33] .Novel Radiation Hardening Read/Write Circuits Using Feedback Connections for Spin–Orbit Torque M...:IEEE Transactions on Circuits and Systems I: Regular Papers,2019,66(5):1853 - 1862
[34] .Spintronic Processing Unit in Spin Transfer Torque Magnetic Random Access Memory.[J]:IEEE Transactions on Electron Devices,2019,66(4):2017 - 2022
[35] .Spintronic Processing Unit Within Voltage-Gated Spin Hall Effect MRAMs.[J]:IEEE Transactions on Nanotechnology,2019,18:473 - 483
[36] .Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.[J]:IEEE Transactions on Circuits and Systems I: Regular Papers,2018,66(1):215 - 225
[37] .High-Performance in-memory Logic Scheme using Unipolar Switching SOT-MRAM.[C].Palma de Mallorca, Spain:IEEE 22nd International Conference on Nanotechnology (NANO),2022
[38] .Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Stra....[C].Irvine, USA:Proceedings of the Great Lakes Symposium on VLSI,2022:243-248
[39] .A High-Speed CNN Hardware Accelerator with Regular Pruning.[C].Santa Clara, CA, USA:International Symposium on Quality Electronic Design (ISQED),2022
[40] .Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based ....[C].Irvine, CA, USA:IEEE/ACM International Conference on Computer-Aided Design (ICCAD),2017
[41] .Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization.[C].Hong Kong, China:IEEE Computer Society Annual Symposium on VLSI (ISVLSI),2018
[42] .Exploring potentials of NAND-like spintronics MRAM for cache design (Invited).[C].Qingdao, China:IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT),2018
[43] .An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.[C].Boston, MA, USA:IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15),2015
[44] .Design and Optimization of an Area-efficient SOT-MRAM.[C].Xi'an, China:IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC),2019

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