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吴比
( 副研究员 )
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的个人主页 http://faculty.nuaa.edu.cn/wubi/zh_CN/index.htm
副研究员 硕士生导师
招生学科专业:
电子信息 -- 【招收硕士研究生】 -- 集成电路学院
集成电路科学与工程 -- 【招收硕士研究生】 -- 集成电路学院
性别:
男
毕业院校:
北京航空航天大学
学历:
博士研究生毕业
学位:
工学博士学位
所在单位:
电子信息工程学院
办公地点:
将军路校区工程训练中心8312
电子邮箱:
312c97670fdf7f18ad6f804a17b859f044bb5d6020d4f3adb78142f512cc269d1a06a437fae6e172e441386a80700899cf622098c70065fb664e0024e27590e1bd3772742ef6bb8a28e5d7c6eb1efdbb23056fcc7a2be132dc0d6256e7b92e2bfae49702d804afbe613e5f2fb19b06895c3bc69355baaa6bad2973cd0074ba38
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[31] .Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM.[J]:IEEE Transactions on Reliability,2016,65(4):1755 - 1768
[32] .A comparative cross-layer study on racetrack memories: Domain wall vs skyrmion:ACM Journal on Emerging Technologies in Computing Systems (JETC),2019,16(1):1-17
[33] .Write-Efficient STT/SOT Hybrid Triple-Level Cell for High-Density MRAM.[J]:IEEE Transactions on Electron Devices,2020,67(4):1460 - 1465
[34] .An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.[J]:IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2018,26(3):484 - 495
[35] .Multiple modes of perpendicular magnetization switching scheme in single spin–orbit torque devic....[J]:Chinese Physics B,2022,31(10):107501
[36] .Erase-Hidden and Drivability-Improved Magnetic Non-Volatile Flip-Flops With NAND-SPIN Devices.[J]:IEEE Transactions on Nanotechnology,2020,19:446 - 454
[37] .Evaluation of Ultrahigh-Speed Magnetic Memories Using Field-Free Spin–Orbit Torque.[J]:IEEE Transactions on Magnetics,2018,54(11)
[38] .Novel Radiation Hardening Read/Write Circuits Using Feedback Connections for Spin–Orbit Torque M...:IEEE Transactions on Circuits and Systems I: Regular Papers,2019,66(5):1853 - 1862
[39] .Spintronic Processing Unit in Spin Transfer Torque Magnetic Random Access Memory.[J]:IEEE Transactions on Electron Devices,2019,66(4):2017 - 2022
[40] .Spintronic Processing Unit Within Voltage-Gated Spin Hall Effect MRAMs.[J]:IEEE Transactions on Nanotechnology,2019,18:473 - 483
[41] .Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.[J]:IEEE Transactions on Circuits and Systems I: Regular Papers,2018,66(1):215 - 225
[42] .High-Performance in-memory Logic Scheme using Unipolar Switching SOT-MRAM.[C].Palma de Mallorca, Spain:IEEE 22nd International Conference on Nanotechnology (NANO),2022
[43] .Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Stra....[C].Irvine, USA:Proceedings of the Great Lakes Symposium on VLSI,2022:243-248
[44] .A High-Speed CNN Hardware Accelerator with Regular Pruning.[C].Santa Clara, CA, USA:International Symposium on Quality Electronic Design (ISQED),2022
[45] .Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based ....[C].Irvine, CA, USA:IEEE/ACM International Conference on Computer-Aided Design (ICCAD),2017
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