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陈鑫
教师个人信息组件组件异常，错误标识码g1xDk, 请查看错误日志
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[1] .Triple-node-upset self-recoverable latch design for aerospace applications:Microelectronics Reliability,2024
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[2] .Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Appli:IEEE Transactions on Circuits and Systems--I: Regular Papers,2024
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[3] .Double-Node-Upset Self-Recoverable Latch Design for Wide Voltage Range Application:IEEE Transactions on Circuits and Systems II: Express Briefs,2023
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[4] .Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS:IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2023
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[5] .FPGA Design of Blind Zone-Suppressed Phase Frequency Detector via Reset Mask and Edge Recovery Opera:Circuits, Systems, and Signal Processing,2023
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[6] Bai Y,,Chen X.A Novel Latch Circuit Against Single Event Upset:AIEA，IEEE CS CPS,2020:500-503
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[7] .Implementation of Highly Reliable Convolutional Neural Network with Low Overhead on Field-Programmab:Electronics,2024
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[8] .SEU/SET Evaluation of Digital VLSI Design from Register Transfer Level to Layout Level:2023 7th International Conference on Electrical, Mechanical and Computer Engineering (ICEMCE),2023
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[9] .Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection:Journal of Electronic Testing,2023
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[10] .FPGA-Based Cross-Hardware MBU Emulation Platform for Layout-Level Digital VLSI:2023 IEEE 32nd Asian Test Symposium (ATS),2023
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[11] .FPGA architecture for convolutional neural network training:Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023),2023
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[12] Zhang Y,,Chen X , Yao J.A compact ultra‐wideband receiving antenna for monitoring applications:Microwave and Optical Technology Letters,2022,64(1):142-148
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[13] Zhang Y,,Ge M , Chen X.Blinding HT: Hiding Hardware Trojan signals traced across multiple sequential levels:IET Circuits, Devices & Systems,2022,16(1):105-115
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[14] 陈鑫,,石东,张颖.基于FPGA的JPEG图像数字水印系统:数据采集与处理,2022,37(01):240-246
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[15] Chen Xin(Teacher),,Xl A , Ys A.Z-domain model procedure for heterodyne digital optical phase-locked loop:Optik,2021,241:167-173
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[16] Chen Xin(Teacher),,Liu X , Zhang Y.Z-domain Modeling Methodology for Homodyne Digital Optical Phase-locked Loop:IEICE Electronics Express,2021,18(10):20210078-20210078
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[17] Lu Y,,Chen X , Zhai X.A Fast Simulation Method for Analysis of SEE in VLSI:Microelectronics Reliability,2021,120:114-110
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[18] Kai Chen,,Xin Chen; Ying Zhang; Zhiwei Zhang.A Rapid Evaluation Technology for SEU in Convolutional Neural Network Circuits:2021 IEEE 3rd International Conference on Circuits and Systems(ICCS),2021:19-23
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[19] Jianpeng Cao,,Xin Chen; Yuxin Bai; Ying Zhang; Tao Liu; Lei Wang.High-Resolution Single Event Transient Measurement Circuit with Low Area Cost:2021 IEEE 3rd International Conference on Circuits and Systems(ICCS),2021:36-40
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[20] Yongxin Shan,,Xin Chen; Xiaoyu Liu; Ying Zhang; Liping Ma.Simulation Framework of Digital Optical Phase-Locked Loop Model in Verilog HDL:2021 IEEE 3rd International Conference on Circuits and Systems(ICCS),2021:83-87
