Chen Xin
Associate Professor
Supervisor of Master's Candidates
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Paper Publications
[11].FPGA architecture for convolutional neural network training:Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023),2023
[12]Zhang Y,,Chen X , Yao J.A compact ultra‐wideband receiving antenna for monitoring applications:Microwave and Optical Technology Letters,2022,64(1):142-148
[13]Zhang Y,,Ge M , Chen X.Blinding HT: Hiding Hardware Trojan signals traced across multiple sequential levels:IET Circuits, Devices & Systems,2022,16(1):105-115
[14]陈鑫,,石东,张颖.基于FPGA的JPEG图像数字水印系统:数据采集与处理,2022,37(01):240-246
[15]Chen Xin(Teacher),,Xl A , Ys A.Z-domain model procedure for heterodyne digital optical phase-locked loop:Optik,2021,241:167-173
[16]Chen Xin(Teacher),,Liu X , Zhang Y.Z-domain Modeling Methodology for Homodyne Digital Optical Phase-locked Loop:IEICE Electronics Express,2021,18(10):20210078-20210078
[17]Lu Y,,Chen X , Zhai X.A Fast Simulation Method for Analysis of SEE in VLSI:Microelectronics Reliability,2021,120:114-110
[18]Kai Chen,,Xin Chen; Ying Zhang; Zhiwei Zhang.A Rapid Evaluation Technology for SEU in Convolutional Neural Network Circuits:2021 IEEE 3rd International Conference on Circuits and Systems(ICCS),2021:19-23
[19]Jianpeng Cao,,Xin Chen; Yuxin Bai; Ying Zhang; Tao Liu; Lei Wang.High-Resolution Single Event Transient Measurement Circuit with Low Area Cost:2021 IEEE 3rd International Conference on Circuits and Systems(ICCS),2021:36-40
[20]Yongxin Shan,,Xin Chen; Xiaoyu Liu; Ying Zhang; Liping Ma.Simulation Framework of Digital Optical Phase-Locked Loop Model in Verilog HDL:2021 IEEE 3rd International Conference on Circuits and Systems(ICCS),2021:83-87
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