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所属单位：电子信息工程学院

发表刊物：IEICE ELECTRONICS EXPRESS

关键字：MISTY1 RAM FPGA LUTs

摘要：This letter proposes highly efficient MISTY1 8-rounds pipe-lined architecture for wireless networks. A novel methodology is adopted for implementation of MISTY1 substitution functions by optimizing S9 and S7 LUTs (Look-Up Tables) to minimize the silicon area. Besides, a key module FI function is compliant to double edge-trigger the optimized S9 LUTs. This leads to substantial reduction in the pipeline requirements for the proposed hardware architecture. For path delay reduction, logic modifications are made in FI and FO functions realizing efficient and high-speed MISTY1 implementation. FPGA implementation on Xilinx FPGA, Virtex 7 xc7vx690t yielded a throughput value of 16.3 Gbps covering area of 1265 CLB slices.

ISSN号：1349-2543

是否译文：否

发表时间：2017-09-25

合写作者：Yasir,陈鑫,Yahya, Muhammad Rehan,Zhang, Xiaoqiang

通讯作者：吴宁