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所属单位：信息化处（信息化技术中心）

发表刊物：Proc. ACM Great Lakes Symp. VLSI GLSVLSI

摘要：Approximate computing is an emerging approach for designing high performance and low power arithmetic circuits. The logarithmic multiplier (LM) converts multiplication into addition and has inherent approximate characteristics. A method combining the Mitchell’s approximation and a dynamic range operand truncation scheme is proposed in this paper to design non-iterative and iterative approximate LMs. The accuracy and the circuit requirements of these designs are assessed to select the best approximate scheme according to different metrics. Compared with conventional non-iterative and iterative 16-bit LMs with exact operands, the normalized mean error distance (NMED) of the best proposed approximate non-iterative and iterative LMs is decreased up to 24.1% and 18.5%, respectively, while the power-delay product (PDP) is decreased up to 51.7% and 45.3%, respectively. Case studies for two error-tolerant applications show the validity of the proposed approximate LMs. © 2018 Association for Computing Machinery.

论文类型：论文集

文献类型：C

是否译文：否

发表时间：2018-05-30

合写作者：王成华,刘伟强,Lombardi, Fabrizio

通讯作者：尹培培,王成华,尹培培