Title of Paper:Design of dynamic range approximate logarithmic multipliers

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Affiliation of Author(s):信息化处（信息化技术中心）

Journal:Proc. ACM Great Lakes Symp. VLSI GLSVLSI

Abstract:Approximate computing is an emerging approach for designing high performance and low power arithmetic circuits. The logarithmic multiplier (LM) converts multiplication into addition and has inherent approximate characteristics. A method combining the Mitchell’s approximation and a dynamic range operand truncation scheme is proposed in this paper to design non-iterative and iterative approximate LMs. The accuracy and the circuit requirements of these designs are assessed to select the best approximate scheme according to different metrics. Compared with conventional non-iterative and iterative 16-bit LMs with exact operands, the normalized mean error distance (NMED) of the best proposed approximate non-iterative and iterative LMs is decreased up to 24.1% and 18.5%, respectively, while the power-delay product (PDP) is decreased up to 51.7% and 45.3%, respectively. Case studies for two error-tolerant applications show the validity of the proposed approximate LMs. © 2018 Association for Computing Machinery.

Document Type:C

Translation or Not:no

Date of Publication:2018-05-30

Co-author:Wang Chenghua,Weiqiang Liu,Lombardi, Fabrizio

Correspondence Author:尹培培,王成华,ypp