Title of Paper:Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications

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Affiliation of Author(s):信息化处（信息化技术中心）

Journal:JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY

Key Words:Approximate/inexact computing Floating-point Multiplier Low power

Abstract:Approximate/inexact computing has become an attractive approach for designing high performance and low power arithmetic circuits. Floating-point (FLP) arithmetic is required in many applications, such as digital signal processing, image processing and machine learning. Approximate FLP multipliers with variable accuracy are proposed in this paper; the accuracy and the circuit requirements of these designs are analyzed and assessed according to different metrics. It is shown that the proposed approximate FLP multiplier designs further reduce delay, area, power consumption and power-delay product (PDP) while incurring about half of the normalized mean error distance (NMED) compared with the previous designs. The proposed IFLPM24-15 is the most efficient design when considering both PDP and NMED. Case studies with three error-tolerant applications show the validity of the proposed approximate designs.

Discipline:Engineering

First-Level Discipline:Electronic Science and Techonology

Document Type:J

ISSN No.:1939-8018

Translation or Not:no

Date of Publication:2018-04-01

Co-author:Wang Chenghua,Weiqiang Liu,Swartzlander, Earl E., Jr.,Lombardi, Fabrizio

Correspondence Author:ypp,Weiqiang Liu