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Affiliation of Author(s):电子信息工程学院

Title of Paper:Area-Efficient Architectures of KASUMI Block Cipher

Journal:Saudi Comput. Soc. National Comput. Conf., NCC

Abstract:This paper presents area-efficient hardware architectures of 64-bit block cipher KASUMI for network security and cryptographic applications. The proposed designs exploit the rolling characteristic of KASUMI to obtain a single round architecture with optimized KASUMI sub-function FO and key generation / scheduling scheme. The FO / FI function explores 2 × low area design implementations for S9 and S7 substitution functions. The first method formulates 16 × logic expressions of S9 / S7 into a single expression whereas the second scheme is based on the minimum utilization of S9 / S7 logic gates. Hardware implementation on ASIC (Application-Specific Integrated Circuit) 0.18 μm at 1.8V resulted in area-efficient KASUMI architectures consisting of 2487 and 2294 gates with throughput values of 32.4 Mbps and 4.6 Mbps respectively. A detailed performance comparison with existing KASUMI architectures yields that the proposed architectures are the most area-efficient KASUMI implementations till date. © 2018 IEEE.

Translation or Not:no

Date of Publication:2018-12-27

Co-author:Yasir,Yahya, Muhammad Rehan,Bi, Qiangjia

Correspondence Author:吴宁