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Affiliation of Author(s):电子信息工程学院

Title of Paper:Compact Hardware Implementations of MISTY1 Block Cipher

Journal:JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS

Key Words:MISTY1 FO function FI function FL/FL-1 function NESSIE ISO IEC 3gpp UMTS

Abstract:This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 n > 8 rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18 degrees mu m @ 1.8V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper.

ISSN No.:0218-1266

Translation or Not:no

Date of Publication:2018-03-01

Co-author:Yasir,Zhang, Xiaoqiang

Correspondence Author:吴宁,Yasir