Affiliation of Author(s):自动化学院
Journal:电子测量技术
Key Words:HEVC;帧内预测;现场可编程门阵列;硬件加速器;
Abstract:为了满足实时性要求,提出了基于现场可编程门阵列(field-programmable gate array,FPGA)的帧内预测并行化设计架构。通过并行架构来减少运算等待时间,通过查找表简化了参考像素选取过程,通过预测运算单元来降低计算复杂度和硬件实现的难度。实验代码通过Verilog HDL编写,通过Modelsim SE 10.1a进行仿真,并在Xilinx Virtex6 XC6VLX760 FPGA上综合。结果表明,该结构完成32X32块的预测需要570个时钟周期,在100 MHz时钟频率下,可以对60 f/s,分辨率为1 920×1 080的视频帧序列进行实时编码,满足实时性要求。
Translation or Not:no
Date of Publication:2017-09-15
Co-author:夏正鹏
Correspondence Author:lky
Associate Professor
Supervisor of Master's Candidates
Gender:Male
Alma Mater:南京航空航天大学
Education Level:博士毕业
Degree:Doctoral Degree in Engineering
School/Department:College of Automation Engineering
Discipline:Measurement Technology and Instrumentation. Precision Instrument and Machinery
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