High-Performance Parallel Fully Redundant Decimal Multiplier
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所属单位：电子信息工程学院
发表刊物：Tien Tzu Hsueh Pao
摘要：High-performance decimal hardware arithmetic is now a high demand due to the requirement for accurate computation in fields like commercial computing and financial analysis.The performance of fully redundant decimal multiplier is limited because the circuit for fully redundant adder is complex.A modified fully redundant adder based on overloaded decimal digit set (ODDS) and a new decimal reduction tree based on fully redundant ODDS adders are proposed.The signed-digit radix-10 recoding and redundant binary coded decimal (BCD) codes are used for fast partial product generation.A recoding conversion circuit is proposed to generate BCD-8421 product fast.Comparison shows that the delay and area of the proposed decimal multiplier are small. © 2018, Chinese Institute of Electronics. All right reserved.
ISSN号：0372-2112
是否译文：否
发表时间：2018-06-01
合写作者：Zhang, Liu,Dong, Wen-Wen
通讯作者：崔晓平