High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
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所属单位：电子信息工程学院
发表刊物：IEEE TRANSACTIONS ON COMPUTERS
关键字：Parallel decimal multiplication overloaded BCD representation redundant excess-3 code redundant arithmetic
摘要：A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [ 0, 9]. The redundant BCD XS-3 code is adopted to generate the multiplicand multiples in a carry-free manner. The XS-3 coded partial products (PPs) are converted to ODDS PPs to fit binary partial product reduction (PPR). In this paper, a regular decimal PPR tree using ODDS and BCD-4221/5211 codes is proposed; it consists of a binary PPR tree block, a non-fixed size BCD-4221 counter block and a BCD-4221/5211 PPR tree block. The decimal carry-save algorithm based on BCD-4221/5211 is used in the PPR tree to obtain high performance multipliers. Moreover, an improved PPG circuit and an improved parallel prefix/carry-select decimal adder are proposed to further improve the performance of the proposed multipliers. Analysis and comparison using the 45 nm technology show that the proposed decimal multipliers are faster and require less hardware area than previous designs found in the technical literature.
ISSN号：0018-9340
是否译文：否
发表时间：2017-12-01
合写作者：Dong, Wenwen,刘伟强,Swartzlander, Earl E.,Lombardi, Fabrizio
通讯作者：崔晓平