所属单位：自动化学院
发表刊物：Guofang Keji Daxue Xuebao
摘要：To break through the limitations of huge memory space and low evolution speed for complex circuits' evolution, the bitstream relocation and the discrepancy configuration were adopted to improve the efficiency of the evolvable hardware implementation approach based on dynamic partial reconfiguration. Firstly, an evolvable IP core capable of bitstream relocation was customized by using the technology of early stage accession to partial reconfiguration provided by Xilinx. Then the original bitstream files were pre-synthesized to form a partial bitstreams library stored in the CF memory for the system to call. Next, a self-evolving system based on a programmable chip system was built, in which the soft processor, MicroBlaze, was utilized as the evolution controller. And the discrepancy configuration was adopted for the real-time adjustment of the circuit topology of the evolvable IP core. Finally, the system structure and the self-evolving mechanisms were verified by the online evolution of digital image filters implemented on the Xilinx Virtex-5 FPGA(field programmable gate array) development board ML507. Experimental results show that the proposed evolutionary mechanisms can reduce the storage space of bitstream files and can accelerate the speed of evolution significantly. © 2017, NUDT Press. All right reserved.
ISSN号：1001-2486
是否译文：否
发表时间：2017-06-28
合写作者：He, Kun,朱萍,Li, Zengwu,Yang, Yuzhong
第一作者：姚睿
通讯作者：姚睿