Wu Bi
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Paper Publications
Design and Optimization of an Area-efficient SOT-MRAM
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Journal:IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

Place of Publication:Xi'an, China

Abstract:Spin orbit torque magnetic random access memory (SOT-MRAM) has attracted numerous research interests since it promises to overcome the write speed and energy bottlenecks of the conventional STT-MRAM. However, the cell density of SOT-MRAM is constrained due to more access transistors. In this work, we present a NAND-Like architecture for SOT-MRAM with a single transistor and several diodes, as well as a novel adaptive array design based on the proposed cell structure. Compared with the standard SOTMRAM, the proposed SOT-MRAM achieves significant improvement in the cell density by sharing transistors, meanwhile attains a comparable write speed. The overhead of write energy can be compensated by a well-designed write policy.

Indexed by:Essay collection

Document Code:978-1-7281-0286-3

Discipline:Engineering

First-Level Discipline:Electronic Science and Techonology

Document Type:C

Translation or Not:no

Date of Publication:2019-07-08

Included Journals:EI

Personal information

Associate Professor
Supervisor of Master's Candidates

Gender:Male

Alma Mater:北京航空航天大学

Education Level:With Certificate of Graduation for Doctorate Study

Degree:Doctoral Degree in Engineering

School/Department:电子信息工程学院

Discipline:Electrical Circuit and System. Microelectronics and Solid-state Electronics

Business Address:将军路校区工程训练中心8312

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