Affiliation of Author(s):自动化学院
Journal:JOURNAL OF POWER ELECTRONICS
Key Words:Layout design Parasitic capacitance Parasitic inductance Silicon Carbide (SiC)
Abstract:Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.
ISSN No.:1598-2092
Translation or Not:no
Date of Publication:2018-07-01
Co-author:Ma, Ceyu,Zhu, Ziyue,yanyangguang
Correspondence Author:Haihong Qin