Title of Paper:XOR gate based low-cost configurable RO PUF

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Affiliation of Author(s):电子信息工程学院

Journal:Proc IEEE Int Symp Circuits Syst

Abstract:A Physical Unclonable Function (PUF) is often used to uniquely identify an integrated circuit by extracting its internal random differences using so-called Challenge Response Pairs (CRPs). As CRPs include unique information about the underlying hardware variations, PUF design is a promising approach to provide authentication and IP-protection capabilities. In this paper, an XOR-gate-based configurable Ring Oscillator (RO) PUF (denoted as XCRO PUF) is presented. This XCRO PUF can generate more CRPs compared with state-of-the-art PUF designs by using the same number of configurable logic blocks (CLBs) in an FPGA implementation. This design is implemented in the Xilinx Spartan-6 XC6SLX9 FPGAS with fixed locations for the XCROs (placed within a ring to improve its uniqueness). The XCRO PUF shows better uniqueness and reliability than other PUF designs. Moreover, a XCRO PUF consumes only 12.5% of the hardware resources to generate a 1-bit response compared with other CRO PUFs implemented in FPGA. © 2017 IEEE.

ISSN No.:0271-4310

Translation or Not:no

Date of Publication:2017-09-25

Co-author:Wang Chenghua,Weiqiang Liu,O'Neill, Maire,Lombardi, Fabrizio

Correspondence Author:Alla