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所属单位：电子信息工程学院

发表刊物：Dianli Zidonghua Shebei Electr. Power Autom. Equip.

摘要：According to the analysis of time-keeping error generated by synchronous clock device, a design scheme of the synchronous clock device is proposed, which improves time-keeping accuracy through reducing the measurement error. In order to improve the time accuracy of synchronous clock device, the interpolating clock method is adopted to reduce the measurement error of GPS(Global Position System) pulse per second period and the remainder of the mean value of pulse per second is compensated to remove the importing error in mean value calculation. The IP(Intellectual Property) core of high-precision synchronous clock based on AMBA APB bus is designed by the proposed scheme and tested by a SoC(System on Chip) with high-precision synchronous clock constructed by ARM Cortex-M0 in FPGA(Field Programmable Gate Arrays). The testing results indicate that the time synchronization accuracy of the IP core with high-precision synchronous clock designed by the proposed scheme is less than 20 ns and its time-keeping error is within 300 ns per hour. © 2018, Electric Power Automation Equipment Press. All right reserved.

ISSN号：1006-6047

是否译文：否

发表时间：2018-12-10

合写作者：Zhang, Yuanyuan,Zhou, Lei,周芳,葛芬

通讯作者：吴宁