教授 博士生导师
性别:女
毕业院校:中国科学技术大学
学历:硕士研究生毕业
学位:工学硕士学位
所在单位:电子信息工程学院
办公地点:电子信息工程学院楼 438室
联系方式:025-84892403
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所属单位:电子信息工程学院
发表刊物:Saudi Comput. Soc. National Comput. Conf., NCC
摘要:This paper presents area-efficient hardware architectures of 64-bit block cipher KASUMI for network security and cryptographic applications. The proposed designs exploit the rolling characteristic of KASUMI to obtain a single round architecture with optimized KASUMI sub-function FO and key generation / scheduling scheme. The FO / FI function explores 2 × low area design implementations for S9 and S7 substitution functions. The first method formulates 16 × logic expressions of S9 / S7 into a single expression whereas the second scheme is based on the minimum utilization of S9 / S7 logic gates. Hardware implementation on ASIC (Application-Specific Integrated Circuit) 0.18 μm at 1.8V resulted in area-efficient KASUMI architectures consisting of 2487 and 2294 gates with throughput values of 32.4 Mbps and 4.6 Mbps respectively. A detailed performance comparison with existing KASUMI architectures yields that the proposed architectures are the most area-efficient KASUMI implementations till date. © 2018 IEEE.
是否译文:否
发表时间:2018-12-27
合写作者:Yasir,Yahya, Muhammad Rehan,Bi, Qiangjia
通讯作者:吴宁