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Affiliation of Author(s):电子信息工程学院

Title of Paper:RoR: A low insertion loss design of rearrangeable hybrid photonic-plasmonic 6 x 6 non-blocking router for ONoCs

Journal:IEICE ELECTRONICS EXPRESS

Key Words:optical networks on chip (ONoC) non-blocking router silicon photonics optical router

Abstract:Optical networks on chip (ONoC) delivers a promising alternative to meet growing needs of higher bandwidth and low power consumption in manycore processors. Optical routers are the key element in ONoCs that significantly affect the performance of overall network. In this letter, we propose a rearrangeable non-blocking 6 x 6 router (RoR) constructed with 2 x 2 hybrid photonic-plasmonic switching (HPPS) elements. Router architectures with 15 HPPS elements and an optimized design using reduced HPPS elements are presented and analyzed. In optimized form, proposed design consumes only 12 HPPS elements which results in low insertion loss and crosstalk noise in comparison to the unoptimized architecture. We observe up to 50% reduction in switching elements count in comparison to other router architecture of same radix.

ISSN No.:1349-2543

Translation or Not:no

Date of Publication:2019-07-10

Co-author:Yahya, Muhammad Rehan,Yan, Gaizhen,gf,Ahmed, Tanveer

Correspondence Author:吴宁